# Introduction to DDR3
The Perf-V development board has a high-speed
onboard. The FPGA and DDR3 SDRAM on the development board are connected to the IO of BANK35. The hardware design of DDR3 requires strict consideration of signal integrity. We have fully considered the matching resistance/terminal resistance, wiring impedance control, and routing in the circuit design and PCB design. Line equal length control ensures the
high-speed and stable operation
of DDR3. DDR3 SDRAM is a common memory, which is widely used in computers and embedded products, such as memory sticks. The working sequence of DDR3 is very complicated. As a very commonly used device, it is not a good choice to consume a lot of manpower and material resources to repeatedly write a driver that meets its working sequence. Among developers, a small number of top developers develop for others. It is a good model for other developers to use these tools to provide users with functions. This is often the case in FPGA development. Xilinx has developed a considerable number of IP cores for its FPGA chips. The simplification of the development difficulty of DDR3 related modules, here we also use this IP core to read and write tests on DDR3.
MIG IP core structure diagram
# Perf-V development board **
Perf-V development board uses Xilinx Artix-7 FPGA chip
. Provides a wealth of peripheral interfaces, including PMOD, Arduino, JTAG, UART interfaces, and high-speed interfaces that can be extended to HDMI, VGA, USB2.0/3.0, camera, Bluetooth, SD card, expansion board, etc, with strong flexibility.
# DDR3 system design
The MIG IP core integrates a storage control module, and only two sets of interfaces are separated externally. One group is used for interactive use between the user and MIG, and the other is used for MIG to interact with DDR3 in accordance with the timing sequence. MIG is equivalent to a console, we no longer need to communicate directly with DDR3, hand over instructions and data to MIG, MIG can complete data storage and reading. Then do a simple data read and write test, write 32 bytes of data to DDR3, and then rewrite the data at this address after the write is completed, if the read data is consistent with the data to be written, the reading and writing test is successful.
DDR3 system design diagram